It is generally desirable to achieve high density, low power consumption, and high-speed operation all in the same memory device. Memory devices having conventional chip architectures typically fall short of these goals, particularly as the requirements for density, power consumption and speed are repeatedly extended.
As shown in FIG. 1, a memory device with conventional chip architecture is indicated generally by the reference numeral 10. The memory device 10 includes a plurality of banks like the bank 11 having a plurality of memory cell array blocks BLK1 through BLKn, a plurality of sub-memory cell array blocks blk1 through blkm, a word line WL and a bit line BL, and a hierarchical data line structure including a long data line from cell to data output buffer, i.e., local input/output (I/O) line pairs LIO and LIOB, global I/O line pairs GIO and GIOB, and data I/O fine pairs DIO and DIOB. The memory device 10 further includes a row decoder 12 for decoding a row address RA from an external applied address, and activating a corresponding word line WL: a column decoder 13 for decoding a column address CA activating a column selection line CSL, and generating a block selection signal B_SEL for selecting a sub-memory cell block blk1 through blkm; and a control unit 14 for interpreting an external command com, and providing a write enable signal WE, a local sense amplifier enable BAR signal /LSA_EN, a load signal Load_sig, a local & global I/O selection signal LGIO_MUX, a global I/O selection signal GIO_MUX and a pre-charge control signal LIOEQ.
For High density, the process is scaled down, and the resulting reduced gate oxide thickness (tox) uses a lowered supply voltage to address reliability concerns. For low power consumption in the presence of the lowered power supply voltage, different supply voltages for the cell array and peripheral circuits may be needed. In the cell array, a lower supply voltage is used for high density and reliability concerns. Conversely, in the peripherals a higher supply voltage is used for high-speed operation. Various problems may arise due to the different supply voltages for the cell array and peripheral circuits, particularly in cases where a current-mode data sense amplifier having a load transistor is used.
For example, an unwanted “read reverse-current” phenomenon may occur during read operations, where current from a peripheral or global I/O may degrade operation of the memory cell array. That is, a weak cell fail or bit line sense amplifier malfunction may occur due to a mismatch of resistors of the cell differential nodes or a threshold voltage (Vt) mismatch of transistors in the bit line sense amplifier. Such a fail or malfunction may be more severe if the voltage difference between the cell array and peripheral is larger.
To address the “read reverse-current” phenomenon, the gate voltage of the multiplexer (MUX) connecting local I/O with global I/O can be controlled or lowered. Unfortunately, lowering the gate voltage of the MUX has the undesirable side effect of degrading write operations. The present disclosure addresses these and other issues.